Xinying Wang (王昕颖)

Ph.D. Candidate

Ph.D. Advisor: Dr. Joseph Zambreno
Reconfigurable Computing Lab
Department of Electrical and Computer Engineering
Iowa State University

Tel: 515-708-1591     Email: xinying "at" iastate.edu

Office: 310 Durham, Iowa State University

Address: ECpE Department, Iowa State University
     2215 Coover Hall
     Ames, IA 50011

 

 

 

 

   

Short Bio:

I am a Ph.D. candidate in Department of Electrical and Computer Engineering at Iowa State University majored in computer engineering. Before joining ISU in 2009, I completed one year M.S. study in Computer System Architecture in School of Computer Science and Engineering at University of Electronic Science of Technology of China (UESTC). I received my B.S. degrees both in Software Engineering and Electrical Communication Engineering at University of Electronic Science and Technology of China (UESTC) in 2008.


Research Interests:

My research interests include Computer Architecture, Reconfigurable Computing, Embedded System Design, High Performance Computing, Software/Hardware co-design for real-world applications such as signal processing, data mining, and machine learning, Software Engineering.


Research Experiences:
 
 
  • Hardware accelerated homotopy l1 minimization process for compressed sensing
  •  (Sep. 2014 - Present)

  • Introduced an FPGA-based architecture for sparse Cholesky Decomposition.
  • Extended the architecture combined with parallel sparse support update to accelerate homotopy l1 minimization for compressed sensing.
 
 
  • FPGA-based Architecture for Efficient Latent Semantic Indexing     
  •  (Nov. 2014 - Present)

  • Extended our hardware architecture for Hestenes-Jacobi algorithm for singular value decomposition.

  • Parallelized the matrix computations with streaming hardware heapsort to perform latent semantic indexing for document classification.

 
 
  • A Configurable Architecture for Sparse LU Decomposition on Matrices with Arbitrary Patterns
  • (Feb. 2014 - Dec. 2014)

  • Presented an efficient architecture for sparse LU decomposition, which can analyze both symmetric and unsymmetric sparse matrices with arbitrary sparsity patterns.

  • The architecture parallelized the computations and pivoting operations with its control logic and resource usage can be configured based on the property of input matrices.
 
 
  • A Reconfigurable Architecture for QR Decomposition Using A Hybrid Approach      
  • (Feb. 2013 - Feb. 2014)

  • Proposed a deeply pipelined reconfigurable architecture that can dynamically configured to perform either Householder transformation or Givens rotation in a manner that takes advantage of the strengths of each.

 

  • At runtime, the input matrix is first partitioned into numerous submatrices. Then, parallel Householder transformations on the sub-matrices in the same column block are performed, which is followed by parallel Givens rotations to annihilate the remaining unneeded individual off-diagonals.
Related papers: ISVLSI 2014 [online]
 
 
  • An FPGA Implementation to Accelerate Singular Value Decomposition       
  • (July 2013 - Feb. 2014)

  • Presented a floating-point Hestenes-Jacobi architecture for Singular Value Decomposition, which is capable of analyzing arbitrary sized matrices.

 

  • Demonstrated improved efficiency of our architecture compared to an optimized software-based SVD solution for matrices with small to medium column dimensions, even with comparably large row dimensions.

Related papers: RAW-IPDPSW 2014 [online]
 
 
  • An Efficient Architecture for Floating-Point Eigenvalue Decomposition      
  • (Aug. 2011 - Jan. 2013)

  • Designed and implemented an efficient FPGA-based double-precision floating-point architecture for Eigenvalue Decomposition, which can efficiently analyze large-scale matrices.

Related papers: FCCM 2014 [online] 


Publications:
Professional Presentations:
Selected Honors:

Last Update: March, 2015